Given how bad the state of FPGA tools are, we'll probably get a super intelligent AGI writing its own self modifying FPGA code before we get good FPGA toolchains for the major vendors...
Its nice we have the handful of Lattice chips with open toolchains, but 9 times out of ten people still use other FPGAs for their reference designs unfortunately.
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Snark aside, FPGAs currently on the market probably can't reprogram while computing (unless its a special hidden feature or something) its not something I've ever seen in documentation that talks about loading the chip configuration at power on time. However at a meta "many FPGA system" level, you could certainly have hardware hot-plug capable systems "offline" a chip unit, reload its code using a hardware management system that looks after this aspect (like using an Lights Out Management system to reboot a racked server in a datacenter)... then power it back up again with the new configuration and it gets added back into the system automatically due to the hot-plug system... so I guess the answer is "yes, but..."
Thanks for the insight. Quite a few things in here I need to read up on.
My naïve thought is some "common high level language" would talk down to the Verilog/VHDL or whatever the FPGA language is and hopefully that is dynamic/modifiable on runtime but doesn't seem to be so.
FPGAs aren't meant to be updated live, so it could be used to represent the reptilian brain of the AGI.
Or say if FPGAs are faster, more compact, or power efficient then the parts of the network that changes slowest could be kept in them to complement the more dynamic parts. I think we still have quite a ways to go before these optimizations since running the network is much easier than training it.
Do FPGAs support any rearranging while working?
Why not having relatively easy hardware (close to Turing Machine) and omnipotent software part? Take in mind that when your AGI starts to enslaving humanity, it will need lots of hardware for the sake of scaling and exotic hardware might be a problem from that point of view.
That could be dumb oversight on my part. If you have large enough processing pool I guess it could be changed to do other things. I just thought FPGAs could do more than that, like you need more RAM? "partition" more.
Adapting software/calculations to common consumer hardware might be easier and more (economically) scalable. Even if perfectly rearranged, FPGAs will have some throughput limit. If computation is the bottleneck, then the quantity of available hardware will be, and unless the AI can access a bunch of reconfigurable FPGAs, there will still likely be many more GPUs available.
Yeah it is true about usually needing something like a "super computer" or at least as you said a lot of GPUs.
I wonder if computation can work on simpler machines, I mean I know that you can condense an ML model and put it on an embedded chip, granted it can't do much/stuck doing that one thing.
Its nice we have the handful of Lattice chips with open toolchains, but 9 times out of ten people still use other FPGAs for their reference designs unfortunately.
...
Snark aside, FPGAs currently on the market probably can't reprogram while computing (unless its a special hidden feature or something) its not something I've ever seen in documentation that talks about loading the chip configuration at power on time. However at a meta "many FPGA system" level, you could certainly have hardware hot-plug capable systems "offline" a chip unit, reload its code using a hardware management system that looks after this aspect (like using an Lights Out Management system to reboot a racked server in a datacenter)... then power it back up again with the new configuration and it gets added back into the system automatically due to the hot-plug system... so I guess the answer is "yes, but..."