I think the XOR (or actually a XNOR) looks far easier to understand if it is drawn symmetrically, like the layout and its logic function suggests:

http://i.imgur.com/OwLkx4A.png

I plan to explain how the 74181 implements its 32 functions and fast carry in a future article, so keep watching.

I look forward to reading that, but meanwhile here is one guide to the 74181 which I found quite lucid (starts near the bottom, continues for 2 more pages --- the rest of the series on ALU design is worth reading too):

http://6502.org/users/dieter/a2/a2_3.htm

The key takeaway from that is, once you decide to make a carry-lookahead adder and compute "G" and "P", and add inversion to one (or both) of the inputs to enable subtraction too, you already have much of what it takes to compute all the logic functions too.

It would be very interesting to have an interview with the original designer(s) of the '181, although from a quick search I can't find exactly who designed it.

I haven't had time to write up my full explanation of the 74181's logical implementation, but I have a summary on stackexchange that you might find interesting: http://electronics.stackexchange.com/questions/1489/what-is-...

The quick summary is the 74181 looks at first like they picked 32 random functions but there's a rational explanation why it has functions like AB PLUS (A OR NOT B). And the gate arrangement makes sense once you realize it's all based on carry-lookahead.

Really enjoyed this article! It seems a bit surprising that 45 year old chips are still available relatively easily.

You are the author? This is spectacular reading. Wonderful work, thank you. I have a question above about the transistor rendering in the second pic but I just now read your stackexchange link and have another question regarding this passage in the SE link:

"The first half of the chip's circuitry computes the four 1-bit sums of A with f(A,B). (Specifically it is creating the Generate and Propagate signals that are used for carry lookahead. This lets the 74181 work in parallel, rather than using a ripple carry.)."

Can you elaborate on "it is creating the Generate and Propagate signals.", I thought that the electrical pulse that drove combinatorial circuit was simply just the clock input on the chip. And that this was propagated to the whole chip instantaneously similar to a broadcast. Do I have this completely wrong?

"Generate" and "Propagate" are referring to the names of the signals in the first stage of a carry-lookahead adder ( https://en.wikipedia.org/wiki/Carry-lookahead_adder ). Generate is A AND B (AB), Propagate is A OR B (A + B). This is also where the AND and OR for the logic functionality comes from.

The '181 has no clock input, the outputs will change after some propagation delay whenever an input changes.

This explanation of CLA adding may also help: https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/look...

I see, this is very interesting. Thanks for the link and explanation.

Good idea on the XOR layout. I've redrawn it to be symmetric. Thanks for the suggestion.

I wired up 8 of these as a 32 bit ALU in preparation of building a digital calculator. The next step was wiring some 16 x 4 RAM chips to create 16 registers and then a set of latches to make an accumulator. I was "this close" to actually having a CPU before I completely ran out of steam on the project.

I just read Code by Petzold last year, and have been meaning to try implementing the minimalistic little "CPU" he develops in the book, in actual hardware, and see if I can make it work. I have no idea how it'll go, but I'm having fun digging into this lower level hardware stuff. I've also been working on building a Z80 based microcomputer, so I can learn more about the low level architecture of a computer. Maybe not very practical, but tons of fun and very educational.

How timely, I was recently looking for a very simple microprocessor made with standard logic and found this: http://www.bradrodriguez.com/papers/piscedu2.htm

It uses four 74181s. I probably won't get around to building one, but it might be fun to write a processor simulator.

I built a matrix multiplier with these (plus a TRW multiplier chip) back in the day. Designed the instruction set and wrote the microcode to implement it. Got it running at 40MHz, which was pretty impressive in 1980. Good times.

Interesting :-) I own several ceramic ones of those. But I'm not planning to use them in the near future, instead my next project will be to create my own ALU using solely with 7400 NAND chips.

You can also go the opposite direction although its much slower by burning 4K eprom (12 bits is 4 bits of A, 4 bits of B, and 4 bits of opcode, 12 bits is a 4K eprom). Both modern eeprom or eprom or especially old eprom will be much slower than the old TTL implementations by maybe a factor of ten.

The interest in this design is modern eproms can be quite large, of course the largest ones are serial which is quite useless for this purpose, but 8 bit ALUs are possible.

It is an interesting approach to build a simple ALU or similar that is worth giving a thought. However, using only NAND gates is more of a fun thing to do :-)

This is really amazing. I have a question I am hoping someone can answer.

In the bottom half of the second picture, in the rendering of the transistor, what is the long thin purple rectangle marked N+ above the P substrate's purpose?

The N+ rectangle near the bottom of the transistor is to reduce resistance because the heavily doped N+ conducts better than lightly doped N. The resistance from the collector through the N region to the junction could be several kohms. The N+ layer reduces this to a few ohms.

Why don't they use N+ instead of N everywhere? Less doping in the collector-base junction improves the breakdown voltage. It's also possible to extend the N+ region under the collector until it meets the buried N+ layer, which reduces resistance even more, but that takes another processing step. So it's all tradeoffs.

Thanks again. I have a tangentially related question if you don't mind. Do you know around when integrated circuits transitioned from using Bipolar Junction Transistor to MOSFET?

It was a gradual transition, with MOS integrated circuits becoming more popular through the 1970s, especially for DRAM and microprocessors. But there were still bipolar RAMs and microprocessors in the mid 1970s.

If you want to do such an analysis by yourself. How do you start and what hardware would you need to achieve such high quality images?

Edit: Nevermind, it's mentioned in the article. I thought you had to grind the layers.

Nice timing - I just bought a couple of these from eBay last week to have a play with.

The fast carry approach is quite interesting